IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH’05)

To be held in conjunction with the VLSI Test Symposium
May 1, 2005

The Lodge at Rancho Mirage, Palm Springs, CA, USA

Advance Program
Introduction - 8:15-8:30
Session 1: Nanoscale Building Block Design - 8:30AM-9:35AM
  • The Vanishing Majority Gate: Trading Power and Speed for Reliability (R)
    V. Beiu, S. Aunet, R. R. Rydberg III, A. Djupdal, and J. Nyathi, Washington State University
  • The Robust QCA Adder Designs using Composable QCA Building Blocks (R)
    Kaijie Wu, University of Illinois at Chicago, Kyosun Kim, University of Incheon, Ramesh Karri, Polytechnic University
  • Yield Analysis and Defect Tolerance of Molecular Crossbars (S)
    Mehdi B. Tahoori, Northeastern University
Break - 9:35AM - 9:50AM
Session 2: Fault and Defect Tolerance Schemes for Nanoscale Computing Systems I - 9:50AM-10:55AM
  • Architectural-level fault tolerant computation in nanoelectronic processors (R)
    Wenjing Rao, Ramesh Karri, Alex Orailoglu, UC San Diego
  • Reliability Analysis of Fault-Tolerant Reconfigurable Architectures (R)
    Debayan Bhaduri and Sandeep Shukla, Virginia Tech
  • Evaluating the Connectivity of Self-Assembled Networks of Nano-Scale Processing Elements (S)
    Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck and Daniel J. Sorin, Duke University
Break - 10:55AM - 11:10AM
Keynote Speaker: Phil Kuekes, HP Labs - 11:10AM-12:00PM
Lunch - 12:00PM - 1:15PM
Session 3: Emerging Nanotechnologies and Circuit Design Styles - 1:15PM-2:35PM
  • An Analysis of Missing Cell Defects in Quantum-Dot Cellular (R)
    Timothy J. Dysart, Mo Liu, Peter M. Kogge, Craig S. Lent, University of NotreDame
  • CMOL (R)
    Jung Hoon Lee, Xialong Ma, Dmitri B. Strukov, and Konstantin K. Likharev, SUNY Stonybrook
  • Analysis of the noise and parameter variations-tolerance of the averaging cell (R)
    Ferran Martorell, Antonio Rubio
  • Nanoscale Spintronic Device Modeling and Logic Circuit Design (S)
    Chao Wang, Qinwei Shi, and Jie Chen, Brown University
Break - 2:35PM - 2:50PM
Session 4: Fault and Defect Tolerance Schemes for Nanoscale Computing Systems II - 2:50PM-3:55PM
  • Achieving Molecular Circuit Robustness Using A Multi-Valued Programmable Logic Model (R)
    Luis E. Cordova, and James P. Davis, Univ of South Carolina
  • On Designing Self-Calibrating Nanoscale Sensors that Adaptively Invest Power for Accuracy (R)
    Darshan D. Thaker, Albert Chen, Rajeevan Amirtharajah and Frederic T. Chong, UC Davis
  • Two-Tier Testing of Circuits with Embedded Nano Blocks (S)
    Lei Fang, Michael S. Hsiao, Virginia Tech
Break - 3:55PM - 4:10PM
Panel: Is nanotechnology all Hype? (or What are critical issues that will make nanoscale systems practical) - 4:10PM-5:30PM
Moderator: Steven Levitan, University of Pittsburgh
Panelists: (to include) James Ellenbogen, MITRE, Mircea Stan, Univ of Virginia, Tom Rust, CTO NANOCHIP, Margarida Jacome, UT Austin
(R) Regular Presentation (25 minutes) (S) Short Presentation (15 minutes)