2nd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 2006)
To be held in conjunction with the International Symposium on Computer Architecture June 17, 2006
Boston Park Plaza Hotel, Boston, MA, USA
Nanoarch 2005
Call for Papers
Sign In

R Karri, Polytechnic U
A Orailoglu, UC San Diego
M. Stan, U Virginia
K. Likharev, Stony Brook
Dan Hammerstrom, Portland State
J. Chen, National Institute of Nanotechnology & U Alberta
S. Levitan, U. Pittsburgh INDUSTRY LIAISON
W. Joyner, SRC
R Kapur, Synopsys
K Kim, Incheon
D. Sorin, Duke
I Bayraktaroglu, Sun

Iris Bahar, Brown
Valeriu Beiu, Washington State
Shamik. Das, MITRE
Andre DeHon, Caltech
Chris Dwyer, Duke
James Ellenbogen, MITRE
Jose Fortes, Univ of Florida
Haldun Hadimioglu, Polytechnic
Niraj Jha, Princeton
Alexander Khitun, UCLA
Yusuf Leblebici, EPFL
Meyya Meyyappan, NASA Ames
Kaushik Roy, Purdue
Alberto Sangiovanni-Vincentelli, UCB
Sandeep Shukla, Virginia Tech
Kang Wang, UC Los Angeles
Kaijie Wu, UIC


Welcome to the Second IEEE International Workshop on Defect-Tolerant Nanoscale Architectures (NANOARCH'06). We envision this NANOARCH to evolve into a forum for all aspects of emerging nanoscale architectures: defect and fault tolerant architectures, emerging computational paradigms for nanoelectronics, modeling and simulation of novel nanoelectronic architectures and concepts, micro-architectural concepts using nanoarchitectural building blocks, dynamic reconfiguration in nanoelectronic architectures, defect and fault models in emerging nanoelectronic device technologies, manufacture testing methodologies for nanoelectronic architectures, yield models, yield analysis and yield enhancement in nanoelectronics, CAD of defect and fault-tolerant nanoelectronic architectures.

The NANOARCH'06 workshop received 31 paper proposals by the abstract deadline and 24 full submissions by the final submission deadline. The program committee conducted a rigorous review process, with each paper receiving at least 5 reviews. Several of the papers received 6 reviews. Based on the comments of the reviewers and the subsequent deliberations of the program committee, we were able to put together an excellent program composed of 7 long paper presentations and 4 short paper presentations, resulting in an acceptance rate of 35.5%. The 7 long papers represent the cross section of the best in the area of nanoscale memory and computing architectures and design methods with a 22.6% acceptance ratio. Some of the accepted papers will be included in a special issue of IEEE Transactions on Nanotechnology. In addition, we are fortunate that Prof. Alain Kaloyeros, President, Albany NanoTech and Chief Administrative Office, College of Nanoscale Science and Engineering, SUNY Albany has agreed to give the keynote.

We would like to thank all members of the program and organizing committee and acknowledge their selfless dedication in helping us in the difficult task of selecting among a set of excellent paper proposals. Most importantly, we would like to thank all of you, the NANOARCH'06 participants, the NANOARCH'06 paper submitters and session chairs, for making NANOARCH a success and establishing it as the pre-eminent forum for exchange of innovative ideas in nanoelectronic architectures and systems. We would like to thank NSF for supporting graduate student travel grants to NANOARCH.

We wish you all a productive time in Boston and hope that you will continue to make NANOARCH a success by actively participating in it, assisting in its organization, and letting us always know when we can do something better. Thank you all for coming.
General Chair Program Chair
Ramesh Karri Alex Orailoglu
Polytechnic University, New YorkUniversity of California, San Diego


Breakfast - 8:00am-8:30am
Introduction to NANOARCH 2006 (General and Program Chair) - 8:30am-8:45am
Session 1: Nanoscale Memory Architectures - 8:45am-10:15am
Session Chair: Mircea Stan, University of Virginia
  • Defect-Tolerant CMOL Memories
    Dmitri B. Strukov and Konstantin K. Likharev
  • Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories
    Fei Sun and Tong Zhang
  • A Fault Tolerant Content-Addressable Memory Cache Architecture for Nanotechnologies
    George Roelke, Rusty Baldwin, Barry Mullins, Yong C.Kim
  • An Investigation into the Maximum Tolerable Error Rate of Majority Gates for Reliable Computation
    Erin R. Taylor, Jie Han, Jos A.B. Fortes (s)
Coffee Break - 10:15am-10:45am
Keynote - 10:45-11:45am
Alain E. Kaloyeros, President, Albany NanoTech and Chief Administrative Officer, College of Nanoscale Science and Engineering (CNSE)
Lunch - 11:45am-1:30pm
Session 2: Nanoscale Design Methods - 1:30pm-2:50pm
Session Chair: Dan Hammerstrom, Portland State University
  • Topology Aware Mapping of Logic Functions onto Nanowire-based Crossbar Architectures
    Wenjing Rao, Alex Orailoglu and Ramesh Karri
  • Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures
    Teng Wang, Mahmoud Bennaser, Yao Guo, Csaba Andras Moritz
  • Building multi-input RTD circuits under reliability constraints (s)
    Viswanath Annampedu and Meghanad D. Wagh
  • Techniques for MRF based implementation of multi-level combinational circuits
    K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, A.Zaslavsky (s)
Break - 2:50pm-3:10pm
Session 3: Nanoscale Architectures - 3:10pm-4:15pm
Session Chair: Dr. Shamik Das, MITRE
  • On Irregular Interconnect Fabrics for Self-Assembled Nanoscale Electronics
    Christof Teuscher
  • Ultralow-Power Adaptive System Architecture Using Complimentary Nano-Electromechanical Carbon Nanotube Switches
    Swarup Bhunia, Massood Tabib-Azar, and Daniel Saab
  • Design and Evaluation of Fail-Stop Self-Assembled Nanoscale Processing Elements
    Jaidev Patwardhan, Chris Dwyer and Alvin Lebeck (s)
Task Force on Nanoelectronics, Nanocomputing and Nanoarchitectures - 4:30pm-5:30pm