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      Important Deadlines:

Submission Deadline:
      August 6th, 2007

Acceptance Notification:
      September 7th, 2007

Final Version of Papers:
      September 17th, 2007


October 21, 2007: Day 1

Opening Remarks: 9:00 AM


Session 1: Reliable NanoArchitectures; 9:15 AM

  1. Dynamic Redundancy Allocation for Reliable and High-Performance Nanocomputing, Shuo Wang, Lei Wang, and Faquir Jain, University of Connecticut (Regular)
  2. Design-Space Exploration of Fault-Tolerant Building Blocks for Large-Scale Quantum Computing.  Tzvetan S. Metodi, Andrew W. Cross, Darshan D. Thaker, Frederic T. Chong, (regular)
  3. A Heterogeneous CMOS-CNT Architecture utilizing Novel Coding of Boolean Functions. Ashish K. Singh, Hady Zeineddine, Adnan Aziz, Sriram Vishwanath and Michael Orshansky, University of Texas at Austin (regular)
  4. Analysis of Defect Tolerance in Molecular Electronics Using Information-Theoretic Measures. Jianwei Dai, Lei Wang, and Faquir Jain, University of Connecticut (short)

Break 1: 10:45 AM


Keynote 1:  Ralph Cavin (SRC), Challenges for Nano-architects; 11:00 AM


Lunch: 12:00 noon


Session 2: Computer-Aided Design and Simulation Techniques for NanoElectronic Devices and Circuits: 1:30 PM

  1. Design Automation for Hybrid CMOS-Nanoelectronics Crossbars. Kyosun Kim, Euncheol Lee, Ramesh Karri, Alex Orailoglu, Incheon University, University of Illinois at Chicago, Polytechnic University, University of California at San Diego (regular)
  2. A Fast, Numerical Circuit-Level Model of Carbon Nanotube Transistor. Tom J Kazmierski, Dafeng Zhou, Bashir M Al-Hashimi and Hamidreza Hashempour, University of Southampton (regular)
  3. A Ballistic Nanoelectronic Device Simulator. Dennis Huo, Qiaoyan Yu, and Paul Ampadu, University of Rochester (regular)
  4. Improving Nanoelectronic Designs Using a Statistical Approach to Identify Key Parameters in Circuit Level SEU Simulations.  Drew C. Ness and David Lilja, University of Minnesota (short)


Poster Session 1: 3:00 PM


Keynote 2: Hugo DeMan (IMEC), On the systemability of ultimate and beyond CMOS technologies, 3:45 PM


Break 2: 4:45 PM

Panel: Funding Needs and Opportunities for Nanoscale electronics 5:00 PM

End of Day 1: 6:30 PM


October 22, 2007: Day 2

Session 3: Defect Tolerant Memories and Circuits; 9:00 AM

  1. A Shift-Register-Based QCA Memory Architecture.  Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, Drexel University (regular)
  2. Thermally-induced soft errors in nanoscale CMOS circuits. H. Li, J. Mundy, W. Patterson, D. Kazazis, A. Zaslavsky and R. I. Bahar, Brown (regular)
  3. Robust Self-Assembly of Interconnects by Parallel DNA Growth. Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi, Northeastern University (regular)
  4. Design of High-Yield Defect-Tolerant Self-Assembled Nanoscale Memories. Girish Venkatasubramanian, P. Oscar Boykin and Renato J. Figueiredo, University of Florida (short)
  5. A Pageable, Defect-Tolerant Nanoscale Memory System. Susmit Biswas, Tzvetan S. Metodi, Frederic T. Chong, Ryan Kastner, University of California at Santa Barbara (short)

Break 3: 10:45 AM


Keynote 3: Meyya Meyyapan (NASA), The Role of Nanotechnology in Shaping Nanoelectronics: An Overview; 11:00 AM


Lunch: 12:00 noon


Session 4: NanoElectronic Circuits; 1:30 PM

  1. Emerging Nanocircuit Paradigm:Graphene-based Electronics for Nanoscale Computing. Z. F. Wang, Huaixiu Zheng, Q. W. Shi, and Jie Chen, University of Alberta (regular)
  2. Combining 2-level Logic Families in Grid-based Nanoscale Fabrics. Teng Wang, Pritish Narayanan, and Csaba Andras Moritz, University of Massachusetts at Amherst (regular)
  3. Prospects for the Development of Digital CMOL Circuits,  Konstantin K. Likharev and Dmitri B. Strukov, SUNY and Hewlett Packard (regular)
  4. Crossbar Latch-based Combinational and Sequential Logic for nano FPGA. Tamer Mohamed, Wael Badawy and Graham Jullien, University of Calgary (short)
  5. Clocking Nanocircuits for Nanocomputers and Other Nanoelectronic Systems.  Shamik Das and Matthew F. Bauwens, MITRE (short)


Poster Session 2: 3:15 PM

Invited Industry session: 4:00 PM

  1. Nanologic(tm): Development of a CMOS-compatible Nanotechnology for the Near-term, Darren K. Brock, Nantero
  2. The Integration of Silicon-Based Molecular Electronic Devices with CMOS: A Hybrid Circuit for On-Chip Characterization,  N. Gergel-Hackett, A.A. Hill, C.A. Hacker, C.A. Richter, Semiconductor Electronics Division, National Institute of Standards and Technology.
  3. Dealing with soft errors in nanometric CMOS, M. Nicolaidis, TIMA/IROC
  4. High Throughput Nanolithography Techniques for Fabricating Hybrid CMOS/Nanowire Cross-Bar Devices, S.V. Sreenivasan, Founder and CTO, Molecular Imprints, Inc.
  5. AC Characterization of Single-walled Carbon Nanotube Field-Effect Transistors, A. Islamshah, Motorola.

Concluding Remarks: 6:05 PM

End of Meeting: 6:15PM

ALL (Regular) talks are 25 minutes and all (Short) talks are 15 minutes. Each Invited Industry Session talk is 25 minutes.