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Important Deadlines:

Submission Deadline:
March 29, 2010

April 5, 2010
Acceptance Notification:
May 10, 2010
Final Version Due:
May 26, 2010
Early Registration:
May 17, 2010

Related Conferences





NANOARCH '10 Advance Program

Day 1: Thursday, June 17, 2010
8:30-8:45 Continental Breakfast
8:45-9:00 Welcome and Introduction
9:00-10:20 Session I (Chair: TBD)
Compact Method for Modeling and Simulation of Memristor Devices (Invited)
Dr. Robinson E. Pino, AFRL
Stochastic Computation With Lattices (Invited)
Prof. Marc Riedel, U. Minn.
Memristor based Programmable Threshold Logic Array (short)
Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, and Garrett S. Rose
10:20-10:40 Break
10:40-12:20 Session II (Chair: TBD)
Toward Logic Fuctions as the Device
Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, and C. Andras Moritz
High Throughput and Low Power Dissipation in QCA Pipelines using Bennett Clocking
Marco Ottavi, Salvatore Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter Kogge, and Fabrizio Lombardi
Fast Equivalence-checking for Quantum Circuits (short)
Shigeru Yamashita and Igor L. Markov
Design and Comparison of NML Systolic Architectures (short)
Michael Crocker, X. Sharon Hu, and Michael Niemier
12:20-1:30 Lunch
1:30-2:30 Keynote:
Kerry Bernstein, IBM
Post-CMOS Nanoarchitectures: A Benchmarking Perspective
(open to all DAC attendees)
2:30-2:45 Break
2:45-4:05 Session III (Chair: TBD)
UNION: A Unified Inter/Intra-Chip Optical Network for Chip Multiprocessors (Invited)
Prof. Jiang Xu, HKUST
Fault Modeling for FinFET Circuits
Muzaffer O. Simsir, Ajay Bhoj, Niraj K. Jha
Reducing transistor count in clocked standard cells with ambipolar double-gate FETs (short)
K. Jabeur, D. Navarro, I. O'Connor, P.E. Gaillardon, M.H. Ben Jamaa, F. Clermidy
4:05-4:30 Break
4:30-5:30 PANEL: CAD for Nanoelectronics
End of Day 1
Day 2: Friday, June 18, 2010
8:15-8:30 Continental Breakfast
8:30-10:20 Session IV (Chair: TBD)
NanoV: Nanowire-Based VLSI Design
Muzaffer O. Simsir, Niraj K. Jha
Artificial Nanoscale Ionic Channels (Invited)
Prof. Luke Theogarajan, UCSB
Nanoscale Neuromorphic Circuits (Invited)
Prof. Yong Chen, UCLA
Stochastic Nanoscale Addressing for Logic (short)
Eric Rachlin and John E. Savage
10:20-10:40 Break
10:40-12:00 Session V (Chair: TBD)
Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications
Michele De Marchi, M. Haykel Ben Jamaa, and Giovanni De Micheli
Design Methodology for Carbon Nanotube based Circuits in the Presence of Metallic Tubes 
Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, and Siva G. Narendra 
Intel LVS Logic as a Combinational Logic Paradigm in CNT Technology (short)
Bao Liu, Zen Cao, Jun Tao, Xuan Zeng, Pushan Tang, Philip H.-S. Wong
12:00-12:15 Presentation of NANOARCH 2010 Best Paper Award
Concluding Remarks