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Conference Venue:
Sheraton Grand Beijing Dongcheng Hotel
36 North Third Ring Road
Beijing, 118305, China
Phone: +86-10-57988888

Important Deadlines:

Submission Deadline:
April 15, 2016
April 22, 2016
April 29, 2016

Acceptance Notification:
May 29, 2016

Final Version Due:
June 7, 2016

Early Registration:
June 7, 2016

July 18-20, 2016



  Day One

9:00 - 9:30


9:30 - 10:30


Maintaining the self-fulfilling prophecy: from dimensional to functional scaling - Dr. Julien Ryckaert (Bio)

10:30 - 11:00

Coffee break


Session I: Circuit design for Emerging technologies

11:00 - 11:30

Dual Reference Sensing Scheme with Triple Steady States for Deeply Scaled STT-MRAM. He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang and Weisheng Zhao.

11:30 - 12:00

Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau and Jean-Michel Portal.

12:00 - 12:15

TFET NDR Skewed Inverter based Sensing Method. Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana and Costin Anghel.

12:15 - 13:45 Lunch

Session II: Tolerant architectures and synthesis methods


Inversion Optimization in Majority-Inverter Graphs. Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarú, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon and Giovanni De Micheli.


A Compare and Select Error Tolerant Scheme for Nonvolatile Processors. Zhibo Wang, Rui Hua, Yongpan Liu and Huazhong Yang.


np-ECC: Nonadjacent Position Error Correction Code for Racetrack Memory. Xiaoyang Wang, Chao Zhang, Xian Zhang and Guangyu Sun.

14:45 - 15:30

Poster Pitch (13 Posters - 3 min pitch)

Towards Automatic Thermal Network Extraction in 3D ICs. Mingyu Li, Jiajun Shi, Mostafizur Rahman, Santosh Khasanvis, Sachin Bhat and Csaba Andras Moritz.

Design of Approximate Redundant Binary Multipliers. Tian Cao, Weiqiang Liu, Chenghua Wang, Xiaoping Cui and Fabrizio Lombardi.

Error Correction Code Protected Data Processing Units. Nicoleta Cucu Laurenciu, Tushar Gupta, Valentin Savin and Sorin Cotofana.

Synthesizing HDL to Memristor Technology: A Generic Framework. Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Said Hamdioui and Koen Bertels.

Energy Management on DVS based Coarse-Grained Reconfigurable Platform. Peng Ouyang, Shouyi Yin, Chunxiao Xing and Shaojun Wei.

SSO-LSM: A Sparse and Self-Organizing Architecture for Liquid State Machine based Neural Processors. Yingyezhe Jin, Yu Liu and Peng Li.

Nonvolatile Online CMOS Trimming with Magnetic Tunnel Junctions. Sumit Dutta, Michael Price and Marc Baldo.

Combining a Volatile and Nonvolatile Memristor in Artificial Synapses Improves Learning in Spiking Neural Network. Mahyar Shahsavari, Pierre Falez and Pierre Boulet.

Evaluation of Spin-Hall-assisted STT-MRAM for Cache Replacement. Liang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang and Weisheng Zhao.

A Supply Voltage-dependent Variation Aware Reliability Evaluation Model. Bo Yang, Michael Quille, Andreas Amann, Sorin Cotofana and Emanuel Popovici.

MECRO: A Local Processing Computer Architecture Based on Memristor Crossbar. Lei Xie and Adib Haron.

Mosaic: A Scheme of Mapping Boolean Non-Volatile Logic on Memristor Crossbar. Lei Xie.

Synthesis of Memristive Circuits Based on Stateful IMPLY Gates using an Evolutionary Algorithm with a Correction Function. Xiaoxiao Wang, Robin Tan and Marek Perkowski.

15:30-16:15 Poster Session
16:15 Session III: Spintronic mutlicontext architectures

Multi-context Non-volatile Content Addressable Memory Using Magnetic Tunnel Junctions. Erya Deng, Guillaume Prenat, Lorena Anghel and Weisheng Zhao.

16:45-17:05 A Memristor-based Compressive Sensing Architecture. Fengyu Qian, Yanping Gong, Guoxian Huang, Kiarash Ahi, Mehdi Anwar and Lei Wang.
17:05-17:20 Accelerate Context Switch by Racetrack-SRAM Hybrid Cells. Weiqi Zhang, Chao Zhang and Guangyu Sun.
End of Technical Session on the First Day
  Day Two
08:30 Session IV: Using stochasticity and randomness

Sleep Stage Classification with Stochastic Bayesian Inference. Laurie Calvet, Joseph Friedman, Damien Querlioz, Pierre Bessière and Jacques Droulez.


A novel circuit design of true random number generator using magnetic tunnel junction. You Wang, Hao Cai, Lirida Naviner, Jacques-Olivier Klein and Weisheng Zhao.


An STT-MRAM Based Strong PUF. Soroush Khaleghi, Paolo Vinella, Soumya Banerjee and Wenjing Rao.

09:50 Session V: All spin logic
09:50-10:20 Improved Circuit Model for All-Spin Logic. Meshal Alawein and Hossein Fariborzi.
10:20-10:35 Ultra-Low Power All Spin Logic Device Acceleration based on Voltage Controlled Magnetic Anisotropy. Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Youguang Zhang and Weisheng Zhao.
10:35-10:50 A spin Hall effect-based multi-level cell for MRAM. Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang and Weisheng Zhao.
10:50-11:15 Coffee break
11:15 AM Session VI: 3D
11:15-11:45 Routability in 3D IC Design: Monolithic 3D vs. Skybridge 3D CMOS. Jiajun Shi, Mingyu Li, Santosh Khasanvis, Mostafizur Rahman and Csaba Andras Moritz.
11:45-12:00 Fine-Grained 3-D CMOS Concept using Stacked Horizontal Nanowires. Naveen Kumar Macha and Mustafizur Rahman.
12:00-13:30 Lunch

Session VII: In-memory computing


Low Power In-Memory Computing Platform with Four Terminal Magnetic Domain Wall Motion Devices. Deliang Fan.


Approximate In-Memory Hamming Distance Calculation with a Memristive Associative Memory. Mohammad M.A. Taha, Walt Woods and Christof Teuscher.


Skeleton-Based Design and Simulation Flow for Computation-In-Memory Architectures. Jintao Yu, Razvan Nane, Muhammad Adib Bin Haron, Said Hamdioui, Henk Corporaal and Koen Bertels.


Memory Processing Unit for In-Memory Processing. Rotem Ben-Hur and Shahar Kvatinsky.


Session VIII: Neuronal and learning approaches


Stochastic Spintronic Device based Synapses and Spiking Neurons for Neuromorphic Computation. Deming Zhang, Lang Zeng, Youguang Zhang, Jacques Klein and Weisheng Zhao.


A Memristor Network with Coupled Oscillator and Crossbar towards L2-norm based Machine Learning. Leibin Ni, Hantao Huang and Hao Yu.


Exploring the Optimal Learning Technique for IBM TrueNorth Platform to Overcome Quantization Loss. Hsin-Pai Cheng, Wei Wen, Chang Song, Beiye Liu, Hai Li and Yiran Chen.


Coffee break


Session IX: Approximate computing


A Comparative Evaluation of Approximate Multipliers. Honglan Jiang, Cong Liu, Naman Maheshwari, Fabrizio Lombardi and Jie Han.


A Fully Parallel Approximate CORDIC Design. Linbin Chen, Fabrizio Lombardi, Jie Han and Weiqiang Liu.


Approximate Computing in MOS/Spintronic Non-Volatile Full-Adder. Hao Cai, You Wang, Lirida Naviner and Weisheng Zhao.

Gala dinner at Bai Jia Da Yuan (Bai Family Mansion)
  Day Three
07:00-12:00 Social event: Great Wall Tour